Native Ethernet RoE mapper/demapper

General Description

Comcores RoE mapper/de-mapper IP core for native Ethernet is a silicon agnostic implementation of the native Ethernet mapping method described in the IEEE 1914.3 standard. The IP-core interfaces to data converters through RAM blocks and can as such be used for multiple different converter interfaces. The data are mapped into one or several 10G Ethernet data streams and vice versa and has been tested with live transfer of I/Q data in frequency domain interfacing to L1 offload engine. The IP-core allows for synchronization from various sources.

Key Features



Delivering Performance
  • Complies with IEEE 1914.3 standard
  • Support multiple antenna data streams of Ethernet
Easy to Use
  • Easy interfacing to standard MAC’s
  • Interfacing all CPRI variants
  • Xilinx VC709 HW demonstration setup available
Silicon Agnostic
  • Designed in VHDL and targeting any RTL implementation like ASICs, ASSPs and FPGAs.

Request datasheet:

  Radio designs
  • Enables Ethernet as a connectivity option for Radio's
  • Used with designs where customer has own proprietary CPRI
  • Transport of frequency domain IQ samples
Baseband designs
  • Enables Ethernet as a fronthaul option
  • Easy integration with legacy CPRI
  • Enables offload of lower level PHY to RRH
  • Fast track testing RoE implmentations


The IP core can be provided as separate blocks or as a subsystem tailored ot your exact application. An extensive documentation that, among others, includes Product Brief, User Manual, Test Environment and test reports is available.

The core will by default come in an encrypted format. Source code option is available.

Pricing and Further Information

Please contact sales for further information about the IP core.

Request quote for the RoE IP core: