Radio over Ethernet Structure Aware Mapper/Demapper

General Description

Comcores Radio Over Ethernet Structure Aware Mapper/Demapper IP core is a silicon agnostic implementation of the structure aware mapping method described in the IEEE 1914.3 standard. The IP-core takes multiple streams of CPRI data and map these into one or several 10G/25G Ethernet data streams and vice versa. The IP-core does as well allow for local injection and retraction of Ethernet traffic.

The IP-core allows easy configuration for various synchronization methods and works with CPRI in both slave and master mode.

The IP-core has been tested successfully in HW and at system level and enables a fast track solution for getting started with this new standard.

Key Features



Delivering Performance
  • Complies with IEEE 1914.3 standard
  • Supports multiple streams of CPRI and Ethernet
  • Complies with CPRI 7.0 standard
  • Configurable for many operating modes
Easy to use
  • HW demonstration setup available
  • Interfacing to all CPRI variants
Silicon Agnostic
  • Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.

Request datasheet:

  Radio designs
  • Enables Ethernet as a connectivity option for Radio's
  • Used with designs where customer has own proprietary CPRI
Baseband designs
  • Enables Ethernet as a fronthaul option
  • Easy integration with legacy CPRI
  • Fast track testing RoE implmentations
  • Many test options available in core


The IP core comes with a solid documentation thatn among othersn includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.

Pricing and Further Information

Please contact sales for further information about the IP core.

Request quote for the RoE IP Core: