Comcores Digital Up Converter (DUC) and Digital Down Converter (DDC) IP core is a silicon agnostic
implementation of a key building block in radio front-end design targeting any ASIC, FPGA or ASSP
technologies. The flexible digital processing architecture enables multi-standard and multi-carrier
operations handling LTE, LTE-A, WCDMA and NR in compliance with 3G, 4G and 5G standards.
The core performs up-and down-conversion of multiple streams of receivers and transmitters signals.
It can dynamically be configured to handle up to 8 transmit paths and 8 receive paths. A total of 8
component carriers per path is supported up to a total aggregated BW of 200 MHz running at a 491,52
It interfaces on one side to DAC’s and ADC’s and on the other side to one or several CPRI, eCPRI, RoE or
xRAN subsystems toward the base station using a standard streaming interface.
Richly featured and highly configurable
- Designed in VHDL and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
Easy to use
- Supporting LTE/LTE-A/WCDMA/NR with 3GPP compliance
- Up to 8 transmit and 8 receive paths
- Supports carrier aggregation of up to 8 component carriers per path
- Aggregated BW of up to 200 MHz
- Multiple interface options such as JESD204B/C toward antennas
and CPRI/eCPRI/RoE/xRAN toward base station
- Number of carriers and antennas are set through generics
- Carrier BW and mix is fully configurable
- Very easy integration with standard AXI4 Lite control interface
- Testbench available for verification
- Powerfull SW setup
Request datasheet: firstname.lastname@example.org
Radio, RRH or DAS
- Wireless base station radio applications
- Increased flexibility and time to market
- Lowers cost of new developments
Software Defined Radio
- Removes a lot of complexity when designing new advanced radio solutions
- Extreme flexibility enables fast track to new radio designs
- Powerfull switching and management of channels
- Extremely flexible data-path processing
The IP core comes with an extensive documentation that, among others,
includes User Manual and Verification Guide. A test bed for injection of traffic and verification of functionality is available for verifying performance.
The core will by default come with an encrypted format. Source code option is available.
Pricing and further information
Please contact sales for further information and discussions about the scope.
Request quote for DUC/DDC IP core: email@example.com