BFP IQ Compression

General Description

The BFP IQ compression IP core is a silicon agnostic implementation of a lossy Block Floating Point compression and de-compression scheme that improves fronthaul bandwidth efficiency.

The IP has been designed to conform with the O-RAN CUS-plane protocol standard v2.0 but can also be used in any arbitrary system where fronthaul bandwidth is a limiting factor. The IP core enables quick and reliable deployment of compression and de-compression at both radio and baseband side and can be configured to handle any kind of fronthaul implementation.

The core can either be used in a 5G/4G radio mode where compression is made on larger blocks, e.g. Resource Blocks, or as a single unit that performs compression on a sample by sample basis.

Key Features



High Performance
  • Compression from 24-bit fixed point IQ to 8-15 bit mantissa + 4 bit exponent
  • Configurable block size for compression
  • Very small silicon footprint
  • Few clock cycles processing latency
Easy to use
  • Matlab evaluation scripts can be provided
  • Easy to configure
  • Standard streaming interface for input/output
Silicon Agnostic
  • Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.

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  Connecting RU with BU
  • Reducing number of fibers deployed or enhancing capacity on existing fibers between Baseband Units and Radio Units
  • Improving capacity and bandwidth efficiency for Ethernet based Baseband and O-RAN Radio Unit connections
Chip-to-chip RU systems
  • Improving bandwidth efficiency for RU multi-chip systems on chip-to-chip links
Test Systems
  • Enabling test of devices deploying IQ compression


The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.

Pricing and further information

Please contact sales for further information about the IP core.

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