u-law IQ Compression
The IQ compression IP core is a silicon agnostic implementation of a compression and de-compression
scheme enabling doubling data capacity on exiting CPRI or Ethernet based links or alternatively running
lower speed links between remote radio units and baseband cards with the same radio ressource capacity.
The compression IP handles any radio channel bandwidth and operates on time-domain IQ samples with
The IP core enables quick and reliable deployment of compression and de-compression at both radio and
baseband side and can be configured to handle any kind of fronthaul implementation.
Easy to use
- Compression better than 50%
- Supports aggregated data rates up to 491.52 Ms/s
- Very low micro-second latency
- Very low EVM degradation
- Matlab test environment can be provided
- Easy configurable
- Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
Request datasheet: firstname.lastname@example.org
Connecting RU with BU
Chip-to-chip RU systems
- Reducing number of fibers deployed or enhancing capacity on existing fibers between Baseband Units and Radio Units
- Improving capacity and bandwidth efficiency for Ethernet based Baseband and Radio Unit connections
- Improving bandwidth efficiency for RU multi-chip systems on chip-to-chip links
- Enabling test of devices deploying IQ compression
The IP core comes deeply verified and with an extensive documentation that, among others,
includes Product Brief and User Manual.
The core will by default come in an encrypted format. Source code option is available.
Pricing and further information
Please contact sales for further information about the IP core.
Request quote for IQ Compression IP core: email@example.com