Comcores offers a variaty of Ethernet Switch IP core for 1G and 10G switching needs.
The switch IP-cores are highly configurable and size optimized implementation
The switches support MAC learning and implement store-and-forward switching approach in order to fulfill
Ethernet standard policy regarding frame integrity checking.
The switches support up to 72 ports where each port provides GMII native interface for Ethernet PHY devices.
The number of ports and rings within the switching fabric are configurable at compile time.
Comcores Lite Ethernet Switch (LES) IP core is a silicon agnostic implementation targeting any ASIC, FPGA
or ASSP technologies.
Ultra Compact Size
- Rings in the switching fabric can be downsized to reduce resource usage at the cost of blocking
- Automatic MAC addresses learning and aging
- Programmable firmware operation with Static or Dynamic (Learning, Aging)
- Full duplex Ethernet interfaces
- GMII interfaces for attaching to an external Physical Layer device (PHY)
Request datasheet: firstname.lastname@example.org
- Up to 73 ports configurable at compile time
- Configurable queuing behavior (round-robin, fair queuing, etc.)
- Support Ethernet Multicast, Broadcast with flooding control to avoid
unnecessary duplication of frames
- Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
The IP cores come deeply verified and with an extensive documentation that, among others,
includes Product Brief and User Manual.
The cores will by default come in an encrypted format. Source code option is available.
Please contact sales for further information about the IP cores.
Request quote for Ethernet Switch IP Cores: email@example.com