Comcores CPRI IP-cores are silicon agnostic implementations of the CPRI standard targeting any
ASIC, FPGA or ASSP technologies. The CPRI IP cores come in several versions to suit any implementation
scenario whether speed, a compact size or a wide feature set is required. The reduced logic consumption, low use of RAM,
the excellent ability to close timing and its extreme flexibility makes the CPRI IP-core a perfect match whether the application
is REC (Radio Equipment Controller) or RE (Radio Equipment). It is designed to deliver on any CPRI application scenario whether this
is RRH, C-RAN switches, Digital Front-End (DFE) processors or advanced test systems. The core can dynamically be configured and can
handle wireless multi-mode radio systems while securing deterministic latency and high-performance throughputs required by LTE-Advanced radio base stations.
Learn more about: CPRI 6.1 IP core
Learn more about: CPRI 7.0 IP core
Comcores Physical Coding Sublayer (PCS) IP cores are
silicon agnostic implementation of the PCS layer described in
IEEE Ethernet standard IEEE 802.3 - 2012 and default
conﬁgured to meet the requirements of CPRI 6.1 or CPRI 7.0.
The PCS IP-cores enable transmission and reception of data via SerDes interfaces. IPs are designed to enable easy upgrade of CPRI 5.0 or older version to run with the highest line-speeds.
The cores can be dynamically conﬁgured to enable either 8B/10B or 64B/66B encoding/decoding. For CPRI 7.0 RS-FEC is included.
To ensure easy integration build-in test capabilities are provided in the core.
Learn more about: CPRI 6.1 PCS IP core
Learn more about: CPRI 7.0 PCS IP core
Learn more about: 1G/2.5G/5G/10G/25G PCS Ethernet and CPRI
Request quote for CPRI IP Core: email@example.com