eCPRI Controller

General Description

Comcores’ eCPRI core is a highly scalable and silicon agnostic implementation of the eCPRI standard targeting any ASIC, FPGA or ASSP technologies. The eCPRI implementation is building on long time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications. The solution is prepared to support both legacy solutions as well new standards making use of L1 offload. The IP is designed to meet or exceed the requirements of radio systems, base band systems, C-RAN switches or advanced test systems. The speed optimized core can handle any solutions reaching from the “small footprint” to the most complex applications running 25 Gbps. The IP can dynamically be configured to handle wireless multi-mode radio systems enabling high-performance throughputs required by 4G and 5G wireless solutions. With the availability of demo platforms Comcores offers a fast track approach to eCPRI bring-up.

Key Features


Block Diagram

Silicon Agnostic
  • Designed in VHDL-2002 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
Richly featured and highly configurable
  • eCPRI Specification V1.1 features implemented
  • All message types supported
  • Prepared for easy integration with SW
  • Supports easy integration with Ehernet MAC and PTP
Easy to use
  • Test bench with typical system configuration and examples

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The IP cores comes with an extensive documentation that among others include Product Brief and User Manual.

The core will by default be delivered encrypted. Source code option is available.

Pricing and further information

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