L1 offload engine

General Description

Comcores L1 offload engine IP's implements split 4 of the proposed NGFI offload scheme and is built for easy interfacing with a native Ethernet RoE mapper/de-mapper. The L1 offload scheme bring down the required fronthaul bandwidth with at least a factor 3 in maximum load scenarios. The flexible interface ensures easy adoption for your specific baseband implementation. The IP-core targets RRH implementations and is coming with a solid simulation environment and demo platform to perform easy validation of the technology. The IP core have been tested in hardware and a demonstrator is available for early proof of concept

Key Features



Delivering Performance
  • Implements LTE Resource mapper, IFFT and CP insertion in DL according to LTE/LTE-A
  • Implements CP removal, FFT, active subcarrier extraction and PRACH detection in UL according to LTE/LTE-A
  • Supports Maximum channels sizes of 20 MHz per channel and have carrier aggreation option to further increase BW
  • Deterministic latency in both DL og UL
  • Very low EVM degradation
Easy to Use
  • Test bed is available
  • Simple straightforward interface allows for easy integration
  • Designed in VHDL and targeting any RTL implementation like ASICs, ASSPs and FPGAs.

Request Datasheet:  info@comcores.com

  • Reduction of fronthaul bandwidth by a factor 3
  • Ethernet based fronthaul


The IP cores can be provided as separate blocks or as a subsystem tailored ot your exact application. An extensive documentation that among others include Product Brief, User Manual, Test Environment and test reports are available.

The core will by default come in an encrypted format. Source code option is available.


Please contact sales for further information about pricing

Request Further Information for Comcores L1 offload solution:  sales@comcores.com