Comcores JESD204B IP core is a silicon proven IP core that deliveres on your exact need for a high speed serial interface for data converters.
The JESD204B IP core comes with the widest parameter set offered in the industry and include RX, TX, mapper and de-mapper as a package or as standalone blocks.
Comcores is offering two basic variants of the core that will address size versus performance tradeoffs for best result no matter what your application is.
Easy to Use
- Designed to JEDEC JESD204B specification
- Line rates from 1 Gb/s to 12.5 Gb/s
- Supports 1-24 lanes
- Supports 1-8 converters
- HD-mode supported
- Performs user-enabled scrambling
- Generates initial lane alignment sequence
- Performs alignment character generation
- Sources link configuration data with user selected parameter values during initial lane synchronization sequence
- Performs the alignment character generation
- Performs 8B/10B encoding
- Optional data mapping and de-mapping
- Supports Subclasses 0, 1 and 2
- Internal clock generation
- HW demonstration platform available
- VIP and regression test suite available
- SerDes interoperability with several major vendors
- Simple test bench is included
- Designed in Verilog and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
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High speed data acquisition systems
- Wireless infrastructure transceiver architectures
- Radar systems
- Software-defined radios
- Portable instrumentation
- Medical ultrasound equipment
- Fewer interconnects on data converters simplifies layout and allows smaller form factor realization without impacting overall system performance.
The IP core comes deeply verified, IOT'ed and with a extensive documentation that among others include Product Brief, User Manual, Verification Guide, Regression Test Environment, Test Cases and test reports.
The core will by default come in an encrypted format. Source code option is available.
Please contact sales for further information about pricing
Request Quote for JESD204B IP Core: firstname.lastname@example.org