Ethernet PCS 1G/2.5G
Comcores PCS IP core is a silicon agnostic implementation of the PCS layer compliant with Ethernet
standard IEEE 802.3-2015. The IP-core supports 1G and 2.5G line rates. The IP provides an interface
between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a Gigabit
Media Independent Interface (GMII) or Serial Gigabit Media Independent Interface (SGMII). On one side it
interfaces to a Serdes device and on the application side it has a port for GMII/SGMII Ethernet signals.
The IP-core is verified using advanced methodologies for RTL design, verification, HW verification and
interoperability testing. It has been optimized for size and is a highly tested solution that will fast track
- Designed to IEEE 802.3-2015 specification
- Low Latency
- Can be used in synchronous Ethernet applications
- Configurable for many operating modes
- IEEE Std. 802.3 Clause 37 Auto-negotiation
- BER test option included
- Loopback at both ends
Request Datasheet: firstname.lastname@example.org
Easy to Use
- MDIO Slave PHY Management interface
- GMII/SGMII interfaces for attaching to Ethernet MAC
- User-friendly application interface
- Designed in VHDL and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
Any 1G/2.5G Ethernet solution
- Fits into solutions where Eth. PCS is needed
The IP core comes deeply verified and with an extensive documentation that, among others,
includes Product Brief and User Manual.
The core will by default come in an encrypted format. Source code option is available.
Pricing and further information
Please contact sales for further information about the IP core.
Request quote for Ethernet PCS IP Core: email@example.com