CPRI 7.0 PCS
Comcores Physical Coding Sublayer (PCS) IP core for CPRI 7.0 is a silicon agnostic implementation of the PCS layer
described in IEEE Ethernet standard IEEE 802.3 - 2012 and default conﬁgured to meet the requirements of
The PCS IP-core enables transmission and reception of data via SerDes interfaces. It is designed to enable
easy upgrade of CPRI 5.0 or older version to run with the highest line-speeds.
The core can be dynamically conﬁgured to enable either 8B/10B or 64B/66B encoding/decoding and includes full RS-FEC functionality
To ensure easy integration build-in test capabilities is provided in the core.
Easy to use
- Complies with CPRI Speciﬁ cation V6.x and V7.0
- Signals can either be 8B/10B or 64B/66B enc/dec
- 64B/66B bus width is fully conﬁ gurable from 10-66 bit.
- Serdes data bus width can be conﬁ gured from 10-40 bits
- Loop back test functionality implemented in core
- Very easy integration with AMBA interfaces
- Build-in test capabilities
- Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
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CPRI IP designs
- A proven interface for upgrading old CPRI controllers
- Used with designs where customer has own proprietary CPRI
The IP core comes deeply verified and with an extensive documentation that among others
include Product Brief and User Manual.
The core will by default come in an encrypted format. Source code option is available.
Please contact sales for further information about pricing
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