CPRI PCS

General Description

Comcores Physical Coding Sublayer (PCS) IP cores are silicon agnostic implementation of the PCS layer described in IEEE Ethernet standard IEEE 802.3 - 2012 and default configured to meet the requirements of CPRI 6.x or CPRI 7.0.

The PCS IP-core enables transmission and reception of data via SerDes interfaces. It is designed to enable easy upgrade of CPRI 5.0 or older version to run with the highest line-speeds.

The cores can be dynamically configured to enable either 8B/10B or 64B/66B encoding/decoding.

For CPRI 7.0 RS-FEC is included.

To ensure easy integration build-in test capabilities is provided in the core.


Key Features

 

Applications

 
Delivering Performance
  • Complies with CPRI Specifi cation V6.x and V7.0
  • Signals can either be 8B/10B or 64B/66B enc/dec
  • 64B/66B bus width is fully confi gurable from 10-66 bit.
  • Serdes data bus width can be confi gured from 10-40 bits
  • Loop back test functionality implemented in core
Easy to use
  • Very easy integration with AMBA interfaces
  • Build-in test capabilities
Silicon Agnostic
  • Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.

Request Datasheet:  info@comcores.com

  CPRI IP designs
  • A proven interface for upgrading old CPRI controllers
  • Used with designs where customer has own proprietary CPRI

Deliverables

The IP core comes deeply verified and with an extensive documentation that among others include Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.

Pricing

Please contact sales for further information about pricing

Request Quote for IQ Compression IP Core:  sales@comcores.com